1. Field of the Invention
This invention relates generally to a semiconductor device and a method of manufacturing the same and more particularly, it relates to an improvement of a method of manufacturing a metal oxide semiconductor (MOS) device which includes self-compensating threshold adjust implants.
2. Description of the Prior Art
As is generally well-known in the art, a semiconductor device having a stacked structure of metal insulator-semiconductor is referred to as a MIS semiconductor device. A transistor which uses an oxide film as the insulator is referred to as MOSFET (Metal Oxide Semiconductor Field Effect Transistor). A typical MOSFET structure includes a pair of source/drain regions (n-type for an N-MOSFET or p-type for a P-MOSFET) formed on a surface of a silicon substrate, a gate oxide film formed on the substrate between the source/drain regions, and a gate electrode formed on the surface of the gate oxide film. The surface area of the substrate between the source region and the drain region is defined as a channel region. The length of the channel region is the distance between the source/drain regions which is typically somewhat shorter than the gate length.
The threshold voltage V.sub.T for the MOSFET device is defined to be the gate-to-source V.sub.gs applied across the gate and source electrodes, below which the MOS device drain-to-source current I.sub.ds becomes near zero. However, this threshold voltage is a function of a number of parameters, which includes the gate material, the gate insulation material, the gate insulation thickness, the channel doping, the impurities at the silicon-insulator interface, and the source-to-substrate voltage between the source and the substrate.
In order to increase the speed of the MOS device, there exists a continuing trend of scaling-down the structure to smaller sizes. One of the ways of scaling is by reducing the length of the gate. However, one of the most pronounced effects occurs due to the gate length reduction is the loss of gate electrode control which is sometimes referred to as threshold (V.sub.T) roll-off. Therefore, in the classical VLSI and integrated circuit design where a very large number of MOSFET devices are fabricated on a plurality of semiconductor integrated circuit dies or chips on a wafer, the distribution of the actual gate length across the wafer will vary due to inescapable process variations. Since the threshold voltage is a function of the gate length, this will also cause the threshold voltages of the various MOS devices on the wafer to be subjected to a wide degree of fluctuation. As a result, the yield for such MOS devices during production will be greatly reduced.
There are known techniques for threshold adjusts which exist in the prior art. For example, in an article entitled "A Novel Source-to-Drain Nonuniformly Doped Channel (NUDC) MOSFET for High Current Drivability and Threshold Voltage Controllability" and authored by Y. Okumura et al., IDEM 90, pp. 391-394, there is described a method of a MOSFET fabrication where the concentration of the channel near the source and drain is increased to suppress the widening of the depletion region and the concentration in the middle of the channel is decreased so as to increase the mobility.
In U.S. Pat. No. 5,466,957 issued on Nov. 14, 1995, to Yuki et al., there is disclosed a semiconductor device which includes a substrate of a first conductivity type, a gate electrode laminated thereon, and source/drain regions of a second conductivity type formed in a self-aligned manner in an upper portion of the substrate outside the gate electrode. A high concentration layer of the first conductivity type is formed in a channel region between the source and drain regions. A low conductivity layer of the first conductivity type is formed between the high conductivity layer and the source/drain regions.
There is also known in the prior art of a technique for controlling the threshold distribution by threshold adjust implant (channel doping at the silicon-insulation interface) prior to the deposition of the gate polysilicon. This classical threshold adjust implant method is described hereinbelow with reference to the fabrication steps shown in FIGS. 1(a) through FIG. 1(f) and labeled as "Prior Art."
In FIG. 1(a), there is illustrated a silicon substrate material 10 which may be of a first conductivity type, in which a threshold adjust implant represented by the solid vertical lines 12 penetrate into the substrate material 10 at an incidence angle of 7.degree. so as to form a higher concentration layer 10a of the first conductivity type. For an NMOS device, the impurity is of the same first conductivity type such as boron (B) or BF.sub.2 while for a PMOS device the impurity is arsenic (As) or phosphorus (P). Typically, the impurity is doped in a dose of approximately 8.times.10.sup.12 ions/cm.sup.2 and at an energy of 5-15 KeV. Then, a gate oxide 14 is grown on the surface of the substrate material 10 having the threshold adjust implant 10a, as shown in FIG. 1(b). Next, a gate electrode 16 comprising polysilicon is deposited on the substrate material 10 over the gate oxide 14 and is patterned using conventional photolithography techniques followed by an anisotropic dry etching, as depicted in FIG. 1(c).
Thereafter, lightly-doped source/drain (LDD) regions 18 with low concentration are implanted at a self-aligning position with the gate electrode 16 on the silicon substrate 10 of the first conductivity type, as shown in FIG. 1(d). For the NMOS device, the impurity is of a second conductivity type such as arsenic ions 19 which are implanted in a dose of 1.times.10.sup.14 to 1.times.10.sup.15 ions/cm.sup.2, at 5 KeV, and an incidence angle of 0.degree. to 7.degree.. After the LDD implant, sidewall spacers 20 serving as insulating films are formed on each side of the gate electrode 16 by etching, as shown in FIG. 1(e). Finally, highly-doped source-drain regions 22 with higher concentration are implanted between LDD regions 18 and the higher concentration layer 10a at self-aligning position with the sidewall spacers 20, as illustrated in FIG. 1(f). For the NMOS device, the impurity is of the second conductivity type, such as arsenic ions 23, which are implanted in a dose of about 2.times.10.sup.15 ions/cm.sup.2, at 5-10 KeV, and an incidence angle of 0.degree. to 7.degree..
Generally, the prior art techniques for threshold adjust suffer from the disadvantages of requiring high energy and high-tilt angle implants. Accordingly, there still exists a need for a method for fabricating MOS devices which have a minimal threshold fluctuation across the semiconductor wafer so as to improve its yield, but yet permits the ability to use low energy and low-tilt angle implants.
The present invention represents a significant improvement over the prior art threshold techniques which provides a method for fabricating MOS devices with an improved threshold roll-off curve. This is achieved in the instant invention by performing an additional threshold adjust implant after the gate is deposited, patterned and etched.